1. Field of the Invention
This invention relates to input buffer circuits for switching an output between HI and LO states when an input signal crosses a threshold level, with a hysteresis function added to prevent unintentional resetting switching of the circuit, and more particularly to Schmitt trigger circuits with a time-variant threshold level.
2. Description of the Related Art
A Schmitt trigger circuit functions as a level-detecting comparator with hysteresis. Its output changes from a LO to a HI state when an increasing input signal crosses an upper switching threshold Vhi, and reverts back to its initial state only when the input crosses a lower threshold level Vlo which is less than Vhi. The difference between the two threshold levels, Vhi-Vlo, is the hysteresis associated with the switch. Schmitt trigger circuits are commonly used on chip inputs to convert a signal with a very slow or sloppy transition into a signal with a sharp transition. They are described, for example, in Glasser et al., The Design and Analysis Circuits, Addison-Wesley Publishing Co., 1985, pages 281-282, and in Hodges et al., Analysis and Design of Digital Integrated Circuits, McGraw-Hill Book Co., 1983, pages 335-337.
A typical input-output voltage characteristic for a non-inverting Schmitt trigger circuit is illustrated in FIG. 1. The output follows a trace 2 when the input rises above the turn-on threshold Vhi, and then follows trace 4 as the input falls back below the turn-off voltage threshold Vlo.
A schematic diagram of a conventional non-inverting CMOS Schmitt trigger is given in FIG. 2. An input signal is applied at an input terminal 2, and is transmitted via an input N-channel field effect transistor (FET) N0pa ("pa" indicates "prior art") to the switch circuit. An ENABLE terminal 4 provides a power conservation function by applying an ENABLE signal to the gates of input transistor N0pa and an ENABLE PMOS transistor P0pa. The source-drain circuit of transistor P0pa is connected between a positive voltage reference Vdd, typically 5 volts, and the input to the switch circuit. Transistor N0pa is turned on and transistor P0pa is turned off when a HI enable signal is applied at terminal 4, allowing the Schmitt trigger to function in the normal manner. A LO enable signal is applied during periods when the output from the Schmitt trigger is not used. It turns transistor N0pa off and transistor P0pa on, tying the Schmitt trigger input to Vdd and causing it to produce a HI output state regardless of the input signal.
The Schmitt trigger itself includes two P-channel FETs P1pa and P2pa, which have their source-drain current circuits connected in series with the source-drain current circuits of a pair of N-channel FETs N1pa and N2pa. The P-channel end of the series circuit is connected to Vdd, while the N-channel end of the circuit is connected to a lower voltage reference such as ground; the input signal is connected in common at node 6 to the gate control electrodes for each of the series-connected FETs. A third P-channel device P3pa has its source-drain circuit connected between ground and the junction 8 of the P1pa/P2pa current circuits, while a third N-channel device N3pa has its source-drain circuit connected between Vdd and the junction 10 of the current circuits for the N-channel devices N1pa and N2pa. The gate electrodes of P3pa and N3pa are connected together to an internal output line 12 at the junction of the current circuits for P2pa and N1pa, which in turn is connected through an inverter INV1 to an external output terminal 14.
In operation, assume that the input signal at terminal 2 is initially LO, and that the circuit has been enabled. The P-channel devices P1pa and P2pa will thus be ON, while the N-channel devices N1pa and N2pa will be OFF. This ties internal output line 12 to a HI state equal to Vdd, which in turn holds P3pa OFF and N3pa ON to set the node 10 HI (less a threshold voltage). The output at terminal 14 at this time is the inverted value of the signal at node 12, or LO.
Assume now that the input voltage at terminal 2 begins to rise. When the input voltage has become great enough, the N-channel devices N1pa and N2pa will become conductive, while the P-channel devices P1pa and P2pa will turn OFF. When it is conductive, FET N2pa connects node 10 to the ground reference, which in turn grounds the internal output line 12 through N1pa; the result is a HI inverted signal at output terminal 14. However, N2pa has to overcome the connection of Vdd to node 10 (through N3pa) before it can place node 10 in a LO state. The relative size scalings of N1pa, N2pa and N3pa are selected to set the threshold voltage level Vhi at which this transition to a HI output occurs. Conversely, once the trigger circuit output is HI, P3pa is held ON by virtue of its gate's ground connection through N1pa and N2pa, while P1pa and P2pa are held OFF. For the circuit output at terminal 14 to revert to a LO state when the input signal at terminal 2 falls, P1pa must become conductive enough to overcome the grounding effects of P3pa and set node 8 at a HI level that corresponds to Vdd. This is the point at which the circuit switches back to a LO output; the relative sizes of P1pa, P2pa and P3pa are selected so that the switching transition occurs at the threshold voltage level Vlo, thus providing the proper amount of hysteresis.
It is not necessary to have both hysteresis transistors P3pa and N3pa. There will still be a level of hysteresis if only one of these transistors is used, but it will be less than with both transistors present. Since the hysteresis level can be doubled using two transistors of the same size, whereas the size of a single transistor has to be substantially more than doubled to double its hysteresis effect, both transistors P3pa and N3pa are commonly employed.
In practice, the circuit does not switch abruptly from one output state to another at the instant Vhi or Vlo is traversed. Rather, a more gradual switching transition takes place, as indicated by the curvatures at either end of switching traces 2 and 4 in FIG. 1, and the non-vertical slope of the traces in between. Also, the actual switching points are sensitive to variations in the manufacturing process, the ambient temperature and the power supply voltage. Such variations impact both the hysteresis and the circuit's speed, as well as its absolute switching points. Thus, in a practical circuit Vhi and Vlo define the outer limits of the input voltage (the threshold window) beyond which the output state will definitely be either HI or LO. For example, with a Vdd of 5 volts and ground providing the voltage reference levels, typical values for Vhi and Vlo are 2.0 volts and 0.8 volts, whereas the actual designed threshold for switching HI might be 1.5 volts and the threshold for switching LO 1.3 volts. This leaves enough "head room" between the designed switching threshold levels and the outer permissible limits of Vhi and Vlo to allow for process, temperature and power supply variations.
The purpose of the hysteresis between the Vhi and Vlo switching threshold levels is to prevent the circuit from unintentionally switching its output state in response to noise or other signal defects. Such unintentional switching is illustrated in FIGS. 3a, 3b and 3c. FIG. 3a illustrates an input signal that begins rising from a LO to a HI state at time T1, and then begins returning to a LO state at time T2. The pulse's rising edge is shown as having a "glitch" 16, during which the signal level momentarily falls before resuming its rise, with another glitch 18 at the end of its falling edge when it rises back above its LO level. The latter glitch can result, for example, from signal undershoots due to transmission line effects from either the circuit board or the bond wires.
The desired output is shown in FIG. 3b, rising from a LO to a HI state at time T1 and then returning to LO at time T2. If, however, the input signal's rising edge initially rises above Vhi but then momentarily falls back below Vlo during the rising edge glitch 16, the buffer circuit will fail by producing an undesired LO output pulse 20, as illustrated in FIG. 3c. Similarly, if the falling edge glitch 18 arises above Vhi after the circuit has resumed a LO output, the circuit will fail by producing an undesired HI pulse 22 after the input pulse has terminated. The input signal is commonly a periodically alternating signal, such as a clock signal, in which the period between successive alternations is known. With such input signals, the circuit failures illustrated in FIG. 3c can reoccur at each alternation in the input signal.
One approach to overcoming this failure problem would be to simply increase the amount of hysteresis by making P3pa and N3pa larger. However, increasing the hysteresis can move the switching points out of the permissible Vhi-Vlo window under certain combinations of processing, temperature and power supply voltage variations. To leave adequate head room between the design switching levels and the window limits to allow for these factors, the amount of hysteresis that can be designed into the circuit is limited.